For digital CMOS logic, when the performance constraints allow, the straightforward solution is to lower the operating voltage, all the way to the Minimum Energy Point (MEP). This point has been proven to exist around 0.3-0.4V depending on various factors. However, due to design difficulties at low operating voltages all commercial microcontrollers (e.g. ARM, EnergyMicro, Texas Instruments) operate at nominal voltage (1-3V) and use power gating to suppress leakage. Naturally, power gating does not bring back the excess energy lost by operating at a voltage point over the MEP. This project designs adaptive processors and systems that operate at the MEP.
Senior Research Fellow, Adjunct prof. of Nanoelectronics and Integrated Digital Systems Design